A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to complementary MOS (CMOS) transistors and bipolar junction transistors (BJT) and their manufacture method.
B) Description of the Related Art
A manufacture method shown in FIGS. 13 to 22 is known as a conventional manufacture method for a bipolar junction transistor (e.g., refer to Japanese Patent Laid-open Publication No. SHO-62-86752 which is incorporated herein by reference).
In the process shown in FIG. 13, in a p-type silicon substrate 1 having a principal surface, an n-type collector region 2 is formed from the principal surface down into the substrate. The n-type well region 2 is formed by the same process as the process of forming an n-type well of a p-channel MOS transistor in a CMOS transistor area. After a field oxide film 3 is formed having an element aperture 3a corresponding to a portion of the collector region 2, a thin oxide film 4 is formed on the silicon surface exposed in the element aperture 3a. The oxide film 3 is formed by the same process as the local oxidation of silicon (LOCOS) process of forming a field oxide film in the CMOS transistor area, and the oxide film 4 is formed by the same process as the thermal oxidation process of forming a gate oxide film in the CMOS transistor area.
Next, in the surface layer of the collector region 2, a p-type active base region 6 is formed by an ion implantation process using a resist layer 5 and the insulating film 3 as a mask. During this process, the CMOS transistor area is masked with the resist layer 5. The ion implantation process includes heat treatment for activating implanted ions, and this heat treatment may be performed after ion implantation is performed once or it may be performed after ion implantation is performed a plurality of times (e.g., after all ion implantation is performed). Description of this heat treatment is omitted unless it is specifically required.
In the process shown in FIG. 14, the oxide films 3 and 4 are selectively etched by using the resist layer 5 as a mask to expose a main surface area of the active base region 6. The resist layer 5 is thereafter removed.
In the process shown in FIG. 15, a polysilicon layer 7A and a silicon oxide layer 8A are sequentially deposited on the substrate by chemical vapor deposition (CVD). Into the polysilicon layer 7A, n-type impurities for forming an emitter region are doped at a concentration of 1021 cm−3 during or after deposition.
In the process shown in FIG. 16, a lamination of the polysilicon layer 7A and silicon oxide layer 8A is patterned in an emitter electrode shape by the etching process using a resist layer (not shown) as a mask, to thereby leave a portion 7 of the polysilicon layer 7A and a portion 8 of the silicon oxide layer 8A in a stacked state.
The processes shown in FIG. 15 and 16 are executed by using the same processes as those of forming a gate electrode in the CMOS transistor area. After the process shown in FIG. 16, in the CMOS transistor area, low concentration (p−-type or n−-type) source/drain regions of at least one of an n-channel and p-channel MOS transistors are formed by using as a mask a gate stacked layer (corresponding to the stacked layer of the polysilicon layer 7 and silicon oxide layer 8).
In the process shown in FIG. 17, on the upper surface of the substrate, a silicon oxide layer 9 is deposited by CVD. In the process shown in FIG. 18, the silicon oxide layer 9 is etched back by reactive ion etching (RIE) to form side wall spacers 9a and 9b on the side walls of the stacked layer of the polysilicon layer 7 and silicon oxide layer 8. The side wall spacers 9a and 9b are both made of the left silicon oxide layer 9. The processes shown in FIGS. 17 and 18 are executed by the same processes as the process of forming a side wall spacer in the CMOS transistor area. The structure having the polysilicon layer 7, silicon oxide layer 8 and side wall spacers 9a and 9b shown in FIG. 18 is hereinafter called an emitter electrode structure 10.
In the process shown in FIG. 19, an n+-type collector contact region 12 is formed in a surface layer of the collector region 2 by an ion implantation process using as a mask a resist layer 11 and an insulating film 3. The n+-type region 12 is formed by using the same process as the ion implantation process of forming n+-type source/drain regions of an n-channel MOS transistor in the CMOS transistor area. After the resist layer 11 is removed, an n+-type emitter region 13 is formed in the surface layer of the active base region 6 by heat treatment for activating implanted ions, by using as a diffusion source the polysilicon layer 7 of the emitter electrode structure 10.
In the process shown in FIG. 20, a p+-type external base region 15 is formed by an ion implantation process using a resist layer 14 as a mask, the external base region overlapping a partial area of the active base region 6. The p+-type region 15 is formed by using the same process as an ion implantation process of forming p+-type source/drain regions of a p-channel MOS transistor in the CMOS transistor area. The resist layer 14 is thereafter removed.
In the process shown in FIG. 21, a silicon oxide layer 16 is deposited on the substrate upper surface by CVD.
In the process shown in FIG. 22, contact holes 16e, 16b and 16c corresponding to the emitter, base and collector are formed through the silicon oxide layer 16. The contact hole 16e corresponding to the emitter is formed in such a manner that the polysilicon layer 7 is exposed by removing the silicon oxide layer 8 of the emitter electrode structure 10. Metal such as Al alloy is coated on the substrate upper surface and the coated layer is patterned to form an emitter electrode layer 17, a base electrode layer 18 and a collector electrode layer 19. The electrode layers 17, 18 and 19 are connected to the polysilicon layer 7, external base region 15 and collector contact region 12, respectively, via the contact holes 16e, 16b and 16c. 
The process shown in FIG. 21 is executed by using the same process as a process of depositing silicon oxide in the CMOS transistor area. The process shown in FIG. 22 is executed by using the same process as a process of forming an electrode in the CMOS transistor area.
The above-described conventional techniques require the processes specific to a bipolar transistor manufacture method (processes unable to use the CMOS transistor processes), i.e., the active base region forming process of FIG. 13 and the oxide film removing process of FIG. 14, and have an increased number of processes.
During a dry etching for patterning the stacked layer of the polysilicon layer 7 and silicon oxide layer 8 in the process shown in FIG. 16, the surface of the active base region 6 is exposed to etching and damaged. Therefore, as the emitter region 13 is formed in the surface layer of the active base region 6 as shown in FIG. 19, leak current at the pn junction (emitter-base junction) between the emitter region 13 and base region 6 increases and a current amplification factor hFE lowers.